At Revasum we make the equipment that is used to make microelectronics. Not just your everyday computer chips, but the sensors, LEDs, RF devices and power devices consumed by the IoT, iPhones, fitbits, automotive, 5G and industrial applications.
OUR WAFER PROCESSING PORTFOLIO
At Revasum, we support a portfolio of production proven, reliable wafer processing equipment for device and substrate manufacturing. Following is a short introduction to CMP, Grinding, and Substrate Manufacturing.
For both dielectric and metal removal and maintaining flat (planar) surfaces, chemical mechanical planarization (CMP) is a critical process. CMP emerged as a necessary process to keep layers planar for subsequent lithography steps as depth-of-field limitations impact yield. A typical IC can have from 3 – 20 layers, each requiring a CMP step to advance further processing. This makes CMP a key, and large segment of semiconductor equipment industry. CMP processes continue to grow in importance for semiconductor manufacturing.
Our grinders are designed to provide high reliability and consistent performance at a low cost of ownership. Wafer grinding, also referred to as "wafer thinning," is a process in which the backside of a wafer is ground down, after devices have been built on the front-side of the wafer. Often, backside thinning is the last step before singulation and packaging -- producing a thinner wafer that allows more layers and a higher density of integrated circuits to fit in a smaller package. For other applications, wafer grinding is an intermediary step before metallization and etch, or other subsequent processing.
The substrate is the basis for all device manufacturing. Many different materials are used as substrates, including silicon, silicon carbide, gallium arsenide, indium phosphide, gallium nitride, quartz, aluminum nitride, sapphire and germanium, with the largest market being prime silicon.
All substrates must be super flat, with an ultra-smooth surface, and free of defects. Defects in the substrate create problems with EPI deposition and correlate to lower device yield.
Conventional processing of substrates involves double-side, batch lapping, and batch polishing to achieve an epi-ready surface. Some hard materials, such as SiC and sapphire, traditionally require diamond polishing.
Revasum offers fully-automated, single wafer processing equipment that provides better control over TTV, shorter processing times, reduced sub-surface damage, smoother surface, and improved wafer-to-wafer consistency compared to batch processing.
Our highly skilled engineers are the keystone to our equipment quality and performance.
We support our worldwide customer base through direct and representative sales and service offices located in the United States, China, France, Germany, Russia, Italy, Israel, Japan, Korea, Taiwan, and the United Kingdom.
Our core strengths are in CMP for 200mm and below, Grinding of hard materials and Si prime wafer polishing. Together, this mix of established and newer technologies addresses several of the process steps needed to manufacture microelectronics.
Revasum’s headquarters are located at 825 Buckley Rd, San Luis Obispo, CA. The facility includes about 13,000 square feet of assembly space and 1,200 square feet of cleanrooms (60% Class 100, 40% Class 10).